Great that it works. But no, for theThis workaround has worked well for several virtual machines.
Can this patch be any value from 39-48?
intel-iommu
it can only take 39 or 48 bits for now (it might allow 52 at a later time when 5-level paging is supported by QEMU, but that's for quite specific use cases and one needs the hardware that supports that, but I digress).The only thing that's needed here is that the guest address width (
aw-bits
) is smaller than the host physical address width (see lscpu
for that), so that the read/writes from/to passthrough devices can properly be translated by the hardware.